Open Source · Apache 2.0GitHub ->

RVDon · RISC-V Domain-specific Open Node

Standing on the shoulders of giants
Connecting human wisdom and creativity with circuits

Starting from the open-source Vortex RISC-V GPU, adding hardware-native instructions for the Pairformer module of AlphaFold3 / Protenix--triangle mask matrix multiplication and Flash Attention are no longer software simulations, but first-class citizens on silicon.

Vortex GPU+WGMMA Datapath+PF Extension=RVDon
GitHub Repo Design Consulting

WHY RVDon

Why We Must Do This

Not reinventing the wheel, but building our own telescope on the shoulders of open-source giants

Standing on Giants

Vortex is open source, RISC-V is open source, Protenix is open source. We use others' shoulders to build our own path--and then open source the path too.

Real Silicon, Not Slides

637 lines of VX_tcu_fa.sv, 3-stage pipeline, 16-entry LUT exp approximation--every line of RTL has passed Verilator simulation, 0/128 errors verified.

Open Source as Faith and Strategy

RTL is the blueprint, the chip is the product. Open-sourcing blueprints doesn't harm commercial interests--it eliminates trust costs, attracts FPGA validators, and builds academic influence.

ARCHITECTURE

Chip Architecture Stack

Three layers progressive--from general GPU base to domain-specific instructions

Vortex RISC-V GPGPU

Open-source RISC-V GPGPU Base

Multi-core GPU based on the Vortex open-source RISC-V GPGPU architecture--providing mature WGMMA datapath and thread scheduling infrastructure for RVDon.

L0 · GPU

TCU · WGMMA Pipeline

Tensor Core Unit · WGMMA

Tensor Compute Unit within Vortex Core, providing WGMMA (Warp Group Matrix Multiply-Accumulate)--RVDon PF extension reuses this datapath.

L1 · TCU

PF Extension ISA

Pairformer Extension ISA

PF_TMM / PF_TMM_INC / PF_FLASH_ATTN--natively supporting triangle mask matrix multiplication and Flash Attention in the TCU pipeline, eliminating redundant computation and software masking overhead.

L2 · PF ISA

PAIRFORMER EXTENSION ISA

PF Extension Instruction Set

Natively supporting Pairformer core computation in the TCU pipeline--replacing software masking, eliminating redundancy

Pairformer Core Computation Patterns

🔺

Triangle Multiplication

Triangular matrix multiplication + symmetry masking--half the computation is redundant on general GPUs, PF_TMM hardware triangle masking skips it directly

⚡

Triangle Attention

Triangular attention + causal masking + online Softmax--FA_SOFTMAX completes within the TCU pipeline, no global synchronization needed

funct3=3✅ RTL + SimX

PF_TMM

Outgoing triangle mask matrix multiplication (Triangle Multiplication Outgoing)

funct3=4✅ RTL + SimX

PF_TMM_INC

Incoming triangle mask matrix multiplication (Triangle Multiplication Incoming)

funct3=5✅ RTL 0/128

PF_FLASH_ATTN

Flash Attention (FA_MMA / FA_SOFTMAX / FA_UPDATE sub-operations)

funct3=-⏸ reserved

PF_SLOAD

Strided Load--reserved for future extension

Full architecture spec -> ARCHITECTURE.md

PROGRESS

Development Progress

Every step passed simulation--0/128 errors means complete

Phase 1.0PF_TMM RTL0/128 errors
Phase 1.1VX_tcu_fa.sv 637 linesFA Online Softmax pipeline
Phase 2.1Pipeline timing alignmentfa_p_delay_pipe
Phase 2.3FP32 arithmetic fixfp32_sub + fp32_floor_int
Phase 2.4FA_SOFTMAX validation0/128 errors ✅
Phase 3FPGA prototype validationNext step

OPEN SOURCE

Open Source Strategy · Open Design · Free Use

All Apache 2.0--design, code, documentation, freely usable, modifiable, and commercializable by anyone

RTL Code + SimX Model

Apache 2.0

RVDon PF extension RTL (VX_tcu_fa.sv etc.) and SimX behavioral model (tcu_unit.cpp) on top of Vortex, open-sourced under Apache 2.0. Anyone can use, modify, and commercialize--but must retain attribution and patent grant terms.

PF Intrinsics + Test Framework

Apache 2.0

vx_pf.h header defining PF extension intrinsics (pf_tmm_sync / pf_tmm_inc_sync / fa_mma_sync etc.) and regression test framework, also released under Apache 2.0--complete toolchain open source.

Architecture Docs + Design Reports

Apache 2.0

ARCHITECTURE.md specification (PF extension ISA, register mapping, programming model) and docs/ design documents, phase reports all open source--letting the community understand the intent of every signal line.

Mandatory Attribution Clause

All derivative works (hardware, software, documentation) must include the following attribution in NOTICE / README / product documentation:

Based on DiVo Gen²AI RVDon (RISC-V Domain-specific Open Node) by 王觉菊 Jueju.Wang, https://github.com/sealionking/rvdon

RVDon, DiVo, Gen²AI are project self-names--the code is yours, the attribution is ours.

BUSINESS

Two-Layer Value Loop

Open source builds brand -> consulting earns revenue

Open Source Layer

RVDon PF extension RTL + SimX behavioral model + intrinsics + regression tests--hardware developers can freely use, modify, and build their own Pairformer accelerators

Community co-building, brand penetration

Consulting Layer

Chip design consulting--from architecture selection to PF extension RTL customization, helping clients optimize Pairformer / Attention acceleration on the RVDon base

Paid service, 1-on-1 customization

CONSULTING

Chip Design Consulting · Verification · Lectures

Domain expert drives AI engineering--not teaching you how to use AI to write RTL, but teaching you how to define chip requirements for AI to execute

1/10 engineer cost

Design Consulting & Customization

From architecture selection to RTL customization, at 1/10 the cost of human IC engineer hours. Upfront consulting ¥30,000 + project startup ¥20,000, fully deductible against design fees--¥50,000 offsets ¥500,000 of human engineer hours.

4× cross-validation

Independent Verification

Using rvdon-kahan software probe to verify hardware authenticity--4 independent dataset implementations with differences within acceptable range, ensuring it's not "The Emperor's New Clothes". You should worry only if different engineers produce identical data.

Methodology + Workshops

University Lectures

For IC majors at universities and vocational colleges, teaching the methodology of "how domain experts define chip requirements for AI to execute"--not "how to use AI to write RTL", but "how to know what a chip should do".

Verification Methodology: Software Probe

If rvdon-kahan can run normally through RVDon's API and achieve expected precision improvement, it proves the hardware interface truly exists. Different engineers writing verification scripts with the same SDK produce results with minor differences within reasonable range--this is evidence of authenticity. Identical data from different engineers is what should worry you.

IP Ownership & Revenue Share

Core IP belongs to the original algorithm creator. DiVo requires an additional 5% "Creative Calibration & Adaptation Revenue Share"--creative ideas are not always engineering-sound and need adaptation to become implementable.

ECOSYSTEM

From Silicon to Targets

RVDon is not an isolated hardware project--it is the bottommost layer of the DiVo bio-computing full stack

RVDon PF Extension->Protenix Structure Prediction->pMHC 3D Structure->Neoantigen / CAR-T

Pairformer is the core module of AlphaFold3 / Protenix. RVDon's PF extension instructions accelerate triangle matrix multiplication and Flash Attention at the silicon level, directly boosting Protenix inference throughput--and Protenix is the engine for DiVo's neoantigen pipeline S5 (pMHC structure prediction) and CAR-T pipeline CT5 (structure validation). From hardware instructions to patient targets, this is a complete causal chain.

Neoantigen mRNA Vaccine CAR-T Cell Therapy pMHC Structure Prediction

Build Your Device with RVDon

Take the open-source design to build your own hardware--or have us customize your domain-specific chip.

View Open Source RepoChip Design Consulting